
circular_singly:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400538 <_init>:
  400538:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40053c:	910003fd 	mov	x29, sp
  400540:	9400003a 	bl	400628 <call_weak_fn>
  400544:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400548:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400550 <.plt>:
  400550:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400554:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xf79c>
  400558:	f947fe11 	ldr	x17, [x16, #4088]
  40055c:	913fe210 	add	x16, x16, #0xff8
  400560:	d61f0220 	br	x17
  400564:	d503201f 	nop
  400568:	d503201f 	nop
  40056c:	d503201f 	nop

0000000000400570 <malloc@plt>:
  400570:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400574:	f9400211 	ldr	x17, [x16]
  400578:	91000210 	add	x16, x16, #0x0
  40057c:	d61f0220 	br	x17

0000000000400580 <__libc_start_main@plt>:
  400580:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400584:	f9400611 	ldr	x17, [x16, #8]
  400588:	91002210 	add	x16, x16, #0x8
  40058c:	d61f0220 	br	x17

0000000000400590 <__gmon_start__@plt>:
  400590:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400594:	f9400a11 	ldr	x17, [x16, #16]
  400598:	91004210 	add	x16, x16, #0x10
  40059c:	d61f0220 	br	x17

00000000004005a0 <abort@plt>:
  4005a0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005a4:	f9400e11 	ldr	x17, [x16, #24]
  4005a8:	91006210 	add	x16, x16, #0x18
  4005ac:	d61f0220 	br	x17

00000000004005b0 <puts@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005b4:	f9401211 	ldr	x17, [x16, #32]
  4005b8:	91008210 	add	x16, x16, #0x20
  4005bc:	d61f0220 	br	x17

00000000004005c0 <printf@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005c4:	f9401611 	ldr	x17, [x16, #40]
  4005c8:	9100a210 	add	x16, x16, #0x28
  4005cc:	d61f0220 	br	x17

00000000004005d0 <putchar@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005d4:	f9401a11 	ldr	x17, [x16, #48]
  4005d8:	9100c210 	add	x16, x16, #0x30
  4005dc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005e0 <_start>:
  4005e0:	d280001d 	mov	x29, #0x0                   	// #0
  4005e4:	d280001e 	mov	x30, #0x0                   	// #0
  4005e8:	aa0003e5 	mov	x5, x0
  4005ec:	f94003e1 	ldr	x1, [sp]
  4005f0:	910023e2 	add	x2, sp, #0x8
  4005f4:	910003e6 	mov	x6, sp
  4005f8:	580000c0 	ldr	x0, 400610 <_start+0x30>
  4005fc:	580000e3 	ldr	x3, 400618 <_start+0x38>
  400600:	58000104 	ldr	x4, 400620 <_start+0x40>
  400604:	97ffffdf 	bl	400580 <__libc_start_main@plt>
  400608:	97ffffe6 	bl	4005a0 <abort@plt>
  40060c:	00000000 	.inst	0x00000000 ; undefined
  400610:	004011d0 	.word	0x004011d0
  400614:	00000000 	.word	0x00000000
  400618:	00401248 	.word	0x00401248
  40061c:	00000000 	.word	0x00000000
  400620:	004012c8 	.word	0x004012c8
  400624:	00000000 	.word	0x00000000

0000000000400628 <call_weak_fn>:
  400628:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xf79c>
  40062c:	f947f000 	ldr	x0, [x0, #4064]
  400630:	b4000040 	cbz	x0, 400638 <call_weak_fn+0x10>
  400634:	17ffffd7 	b	400590 <__gmon_start__@plt>
  400638:	d65f03c0 	ret
  40063c:	00000000 	.inst	0x00000000 ; undefined

0000000000400640 <deregister_tm_clones>:
  400640:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400644:	91012000 	add	x0, x0, #0x48
  400648:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40064c:	91012021 	add	x1, x1, #0x48
  400650:	eb00003f 	cmp	x1, x0
  400654:	540000a0 	b.eq	400668 <deregister_tm_clones+0x28>  // b.none
  400658:	b0000001 	adrp	x1, 401000 <create_circular_link+0x8>
  40065c:	f9417421 	ldr	x1, [x1, #744]
  400660:	b4000041 	cbz	x1, 400668 <deregister_tm_clones+0x28>
  400664:	d61f0020 	br	x1
  400668:	d65f03c0 	ret
  40066c:	d503201f 	nop

0000000000400670 <register_tm_clones>:
  400670:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400674:	91012000 	add	x0, x0, #0x48
  400678:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40067c:	91012021 	add	x1, x1, #0x48
  400680:	cb000021 	sub	x1, x1, x0
  400684:	9343fc21 	asr	x1, x1, #3
  400688:	8b41fc21 	add	x1, x1, x1, lsr #63
  40068c:	9341fc21 	asr	x1, x1, #1
  400690:	b40000a1 	cbz	x1, 4006a4 <register_tm_clones+0x34>
  400694:	b0000002 	adrp	x2, 401000 <create_circular_link+0x8>
  400698:	f9417842 	ldr	x2, [x2, #752]
  40069c:	b4000042 	cbz	x2, 4006a4 <register_tm_clones+0x34>
  4006a0:	d61f0040 	br	x2
  4006a4:	d65f03c0 	ret

00000000004006a8 <__do_global_dtors_aux>:
  4006a8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006ac:	910003fd 	mov	x29, sp
  4006b0:	f9000bf3 	str	x19, [sp, #16]
  4006b4:	d0000093 	adrp	x19, 412000 <malloc@GLIBC_2.17>
  4006b8:	39412260 	ldrb	w0, [x19, #72]
  4006bc:	35000080 	cbnz	w0, 4006cc <__do_global_dtors_aux+0x24>
  4006c0:	97ffffe0 	bl	400640 <deregister_tm_clones>
  4006c4:	52800020 	mov	w0, #0x1                   	// #1
  4006c8:	39012260 	strb	w0, [x19, #72]
  4006cc:	f9400bf3 	ldr	x19, [sp, #16]
  4006d0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006d4:	d65f03c0 	ret

00000000004006d8 <frame_dummy>:
  4006d8:	17ffffe6 	b	400670 <register_tm_clones>

00000000004006dc <display_debug>:
  4006dc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4006e0:	910003fd 	mov	x29, sp
  4006e4:	f9000fa0 	str	x0, [x29, #24]
  4006e8:	f9400fa0 	ldr	x0, [x29, #24]
  4006ec:	f9400000 	ldr	x0, [x0]
  4006f0:	f90017a0 	str	x0, [x29, #40]
  4006f4:	1400000b 	b	400720 <display_debug+0x44>
  4006f8:	f94017a0 	ldr	x0, [x29, #40]
  4006fc:	b9400001 	ldr	w1, [x0]
  400700:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400704:	910be000 	add	x0, x0, #0x2f8
  400708:	2a0103e2 	mov	w2, w1
  40070c:	f94017a1 	ldr	x1, [x29, #40]
  400710:	97ffffac 	bl	4005c0 <printf@plt>
  400714:	f94017a0 	ldr	x0, [x29, #40]
  400718:	f9400400 	ldr	x0, [x0, #8]
  40071c:	f90017a0 	str	x0, [x29, #40]
  400720:	f94017a0 	ldr	x0, [x29, #40]
  400724:	f100001f 	cmp	x0, #0x0
  400728:	54fffe81 	b.ne	4006f8 <display_debug+0x1c>  // b.any
  40072c:	52800140 	mov	w0, #0xa                   	// #10
  400730:	97ffffa8 	bl	4005d0 <putchar@plt>
  400734:	d503201f 	nop
  400738:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40073c:	d65f03c0 	ret

0000000000400740 <reverse_perfect_debug>:
  400740:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400744:	910003fd 	mov	x29, sp
  400748:	f9000fa0 	str	x0, [x29, #24]
  40074c:	f9400fa0 	ldr	x0, [x29, #24]
  400750:	f9400401 	ldr	x1, [x0, #8]
  400754:	f9400fa0 	ldr	x0, [x29, #24]
  400758:	f9400400 	ldr	x0, [x0, #8]
  40075c:	f9400402 	ldr	x2, [x0, #8]
  400760:	f9400fa0 	ldr	x0, [x29, #24]
  400764:	f9400400 	ldr	x0, [x0, #8]
  400768:	f9400400 	ldr	x0, [x0, #8]
  40076c:	f9400403 	ldr	x3, [x0, #8]
  400770:	f9400fa0 	ldr	x0, [x29, #24]
  400774:	f9400400 	ldr	x0, [x0, #8]
  400778:	f9400400 	ldr	x0, [x0, #8]
  40077c:	f9400400 	ldr	x0, [x0, #8]
  400780:	f9400404 	ldr	x4, [x0, #8]
  400784:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400788:	910c2000 	add	x0, x0, #0x308
  40078c:	aa0403e5 	mov	x5, x4
  400790:	aa0303e4 	mov	x4, x3
  400794:	aa0203e3 	mov	x3, x2
  400798:	aa0103e2 	mov	x2, x1
  40079c:	f9400fa1 	ldr	x1, [x29, #24]
  4007a0:	97ffff88 	bl	4005c0 <printf@plt>
  4007a4:	f9400fa0 	ldr	x0, [x29, #24]
  4007a8:	f90017a0 	str	x0, [x29, #40]
  4007ac:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4007b0:	910c6000 	add	x0, x0, #0x318
  4007b4:	f9400fa2 	ldr	x2, [x29, #24]
  4007b8:	f94017a1 	ldr	x1, [x29, #40]
  4007bc:	97ffff81 	bl	4005c0 <printf@plt>
  4007c0:	f9000fbf 	str	xzr, [x29, #24]
  4007c4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4007c8:	910cc000 	add	x0, x0, #0x330
  4007cc:	f9400fa1 	ldr	x1, [x29, #24]
  4007d0:	97ffff7c 	bl	4005c0 <printf@plt>
  4007d4:	14000020 	b	400854 <reverse_perfect_debug+0x114>
  4007d8:	f94017a0 	ldr	x0, [x29, #40]
  4007dc:	f90013a0 	str	x0, [x29, #32]
  4007e0:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4007e4:	910d0000 	add	x0, x0, #0x340
  4007e8:	f94017a2 	ldr	x2, [x29, #40]
  4007ec:	f94013a1 	ldr	x1, [x29, #32]
  4007f0:	97ffff74 	bl	4005c0 <printf@plt>
  4007f4:	f94017a0 	ldr	x0, [x29, #40]
  4007f8:	f9400400 	ldr	x0, [x0, #8]
  4007fc:	f90017a0 	str	x0, [x29, #40]
  400800:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400804:	910d4000 	add	x0, x0, #0x350
  400808:	f94017a2 	ldr	x2, [x29, #40]
  40080c:	f94017a1 	ldr	x1, [x29, #40]
  400810:	97ffff6c 	bl	4005c0 <printf@plt>
  400814:	f94013a0 	ldr	x0, [x29, #32]
  400818:	f9400fa1 	ldr	x1, [x29, #24]
  40081c:	f9000401 	str	x1, [x0, #8]
  400820:	f94013a0 	ldr	x0, [x29, #32]
  400824:	f9400401 	ldr	x1, [x0, #8]
  400828:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  40082c:	910da000 	add	x0, x0, #0x368
  400830:	f9400fa2 	ldr	x2, [x29, #24]
  400834:	97ffff63 	bl	4005c0 <printf@plt>
  400838:	f94013a0 	ldr	x0, [x29, #32]
  40083c:	f9000fa0 	str	x0, [x29, #24]
  400840:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400844:	910e0000 	add	x0, x0, #0x380
  400848:	f94013a2 	ldr	x2, [x29, #32]
  40084c:	f9400fa1 	ldr	x1, [x29, #24]
  400850:	97ffff5c 	bl	4005c0 <printf@plt>
  400854:	f94017a0 	ldr	x0, [x29, #40]
  400858:	f100001f 	cmp	x0, #0x0
  40085c:	54fffbe1 	b.ne	4007d8 <reverse_perfect_debug+0x98>  // b.any
  400860:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400864:	910e6000 	add	x0, x0, #0x398
  400868:	f9400fa1 	ldr	x1, [x29, #24]
  40086c:	97ffff55 	bl	4005c0 <printf@plt>
  400870:	f9400fa0 	ldr	x0, [x29, #24]
  400874:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400878:	d65f03c0 	ret

000000000040087c <reverse_perfect_noreturn_debug>:
  40087c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400880:	910003fd 	mov	x29, sp
  400884:	f9000fa0 	str	x0, [x29, #24]
  400888:	f9400fa0 	ldr	x0, [x29, #24]
  40088c:	f9400002 	ldr	x2, [x0]
  400890:	f9400fa0 	ldr	x0, [x29, #24]
  400894:	f9400000 	ldr	x0, [x0]
  400898:	b0000001 	adrp	x1, 401000 <create_circular_link+0x8>
  40089c:	910ec025 	add	x5, x1, #0x3b0
  4008a0:	a9401003 	ldp	x3, x4, [x0]
  4008a4:	f9400fa1 	ldr	x1, [x29, #24]
  4008a8:	aa0503e0 	mov	x0, x5
  4008ac:	97ffff45 	bl	4005c0 <printf@plt>
  4008b0:	f9400fa0 	ldr	x0, [x29, #24]
  4008b4:	f9400000 	ldr	x0, [x0]
  4008b8:	f90017a0 	str	x0, [x29, #40]
  4008bc:	f9400fa0 	ldr	x0, [x29, #24]
  4008c0:	f9400001 	ldr	x1, [x0]
  4008c4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4008c8:	910c6000 	add	x0, x0, #0x318
  4008cc:	aa0103e2 	mov	x2, x1
  4008d0:	f94017a1 	ldr	x1, [x29, #40]
  4008d4:	97ffff3b 	bl	4005c0 <printf@plt>
  4008d8:	f9400fa0 	ldr	x0, [x29, #24]
  4008dc:	f900001f 	str	xzr, [x0]
  4008e0:	f9400fa0 	ldr	x0, [x29, #24]
  4008e4:	f9400001 	ldr	x1, [x0]
  4008e8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4008ec:	910cc000 	add	x0, x0, #0x330
  4008f0:	97ffff34 	bl	4005c0 <printf@plt>
  4008f4:	14000024 	b	400984 <reverse_perfect_noreturn_debug+0x108>
  4008f8:	f94017a0 	ldr	x0, [x29, #40]
  4008fc:	f90013a0 	str	x0, [x29, #32]
  400900:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400904:	910d0000 	add	x0, x0, #0x340
  400908:	f94017a2 	ldr	x2, [x29, #40]
  40090c:	f94013a1 	ldr	x1, [x29, #32]
  400910:	97ffff2c 	bl	4005c0 <printf@plt>
  400914:	f94017a0 	ldr	x0, [x29, #40]
  400918:	f9400400 	ldr	x0, [x0, #8]
  40091c:	f90017a0 	str	x0, [x29, #40]
  400920:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400924:	910d4000 	add	x0, x0, #0x350
  400928:	f94017a2 	ldr	x2, [x29, #40]
  40092c:	f94017a1 	ldr	x1, [x29, #40]
  400930:	97ffff24 	bl	4005c0 <printf@plt>
  400934:	f9400fa0 	ldr	x0, [x29, #24]
  400938:	f9400001 	ldr	x1, [x0]
  40093c:	f94013a0 	ldr	x0, [x29, #32]
  400940:	f9000401 	str	x1, [x0, #8]
  400944:	f94013a0 	ldr	x0, [x29, #32]
  400948:	f9400401 	ldr	x1, [x0, #8]
  40094c:	f9400fa0 	ldr	x0, [x29, #24]
  400950:	f9400002 	ldr	x2, [x0]
  400954:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400958:	910da000 	add	x0, x0, #0x368
  40095c:	97ffff19 	bl	4005c0 <printf@plt>
  400960:	f9400fa0 	ldr	x0, [x29, #24]
  400964:	f94013a1 	ldr	x1, [x29, #32]
  400968:	f9000001 	str	x1, [x0]
  40096c:	f9400fa0 	ldr	x0, [x29, #24]
  400970:	f9400001 	ldr	x1, [x0]
  400974:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400978:	910e0000 	add	x0, x0, #0x380
  40097c:	f94013a2 	ldr	x2, [x29, #32]
  400980:	97ffff10 	bl	4005c0 <printf@plt>
  400984:	f94017a0 	ldr	x0, [x29, #40]
  400988:	f100001f 	cmp	x0, #0x0
  40098c:	54fffb61 	b.ne	4008f8 <reverse_perfect_noreturn_debug+0x7c>  // b.any
  400990:	f9400fa0 	ldr	x0, [x29, #24]
  400994:	f9400001 	ldr	x1, [x0]
  400998:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  40099c:	910f0000 	add	x0, x0, #0x3c0
  4009a0:	97ffff08 	bl	4005c0 <printf@plt>
  4009a4:	d503201f 	nop
  4009a8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009ac:	d65f03c0 	ret

00000000004009b0 <reverse_debug>:
  4009b0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4009b4:	910003fd 	mov	x29, sp
  4009b8:	f9000fa0 	str	x0, [x29, #24]
  4009bc:	f9400fa0 	ldr	x0, [x29, #24]
  4009c0:	f9001ba0 	str	x0, [x29, #48]
  4009c4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4009c8:	910fa000 	add	x0, x0, #0x3e8
  4009cc:	f9400fa1 	ldr	x1, [x29, #24]
  4009d0:	97fffefc 	bl	4005c0 <printf@plt>
  4009d4:	14000008 	b	4009f4 <reverse_debug+0x44>
  4009d8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4009dc:	910fe000 	add	x0, x0, #0x3f8
  4009e0:	f9401ba1 	ldr	x1, [x29, #48]
  4009e4:	97fffef7 	bl	4005c0 <printf@plt>
  4009e8:	f9401ba0 	ldr	x0, [x29, #48]
  4009ec:	f9400400 	ldr	x0, [x0, #8]
  4009f0:	f9001ba0 	str	x0, [x29, #48]
  4009f4:	f9401ba0 	ldr	x0, [x29, #48]
  4009f8:	f100001f 	cmp	x0, #0x0
  4009fc:	54fffee1 	b.ne	4009d8 <reverse_debug+0x28>  // b.any
  400a00:	52800140 	mov	w0, #0xa                   	// #10
  400a04:	97fffef3 	bl	4005d0 <putchar@plt>
  400a08:	f9400fa0 	ldr	x0, [x29, #24]
  400a0c:	f9400401 	ldr	x1, [x0, #8]
  400a10:	f9400fa0 	ldr	x0, [x29, #24]
  400a14:	f9400400 	ldr	x0, [x0, #8]
  400a18:	f9400402 	ldr	x2, [x0, #8]
  400a1c:	f9400fa0 	ldr	x0, [x29, #24]
  400a20:	f9400400 	ldr	x0, [x0, #8]
  400a24:	f9400400 	ldr	x0, [x0, #8]
  400a28:	f9400403 	ldr	x3, [x0, #8]
  400a2c:	f9400fa0 	ldr	x0, [x29, #24]
  400a30:	f9400400 	ldr	x0, [x0, #8]
  400a34:	f9400400 	ldr	x0, [x0, #8]
  400a38:	f9400400 	ldr	x0, [x0, #8]
  400a3c:	f9400404 	ldr	x4, [x0, #8]
  400a40:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400a44:	91102000 	add	x0, x0, #0x408
  400a48:	aa0403e5 	mov	x5, x4
  400a4c:	aa0303e4 	mov	x4, x3
  400a50:	aa0203e3 	mov	x3, x2
  400a54:	aa0103e2 	mov	x2, x1
  400a58:	f9400fa1 	ldr	x1, [x29, #24]
  400a5c:	97fffed9 	bl	4005c0 <printf@plt>
  400a60:	f9400fa0 	ldr	x0, [x29, #24]
  400a64:	b9400001 	ldr	w1, [x0]
  400a68:	f9400fa0 	ldr	x0, [x29, #24]
  400a6c:	f9400400 	ldr	x0, [x0, #8]
  400a70:	b9400002 	ldr	w2, [x0]
  400a74:	f9400fa0 	ldr	x0, [x29, #24]
  400a78:	f9400400 	ldr	x0, [x0, #8]
  400a7c:	f9400400 	ldr	x0, [x0, #8]
  400a80:	b9400003 	ldr	w3, [x0]
  400a84:	f9400fa0 	ldr	x0, [x29, #24]
  400a88:	f9400400 	ldr	x0, [x0, #8]
  400a8c:	f9400400 	ldr	x0, [x0, #8]
  400a90:	f9400400 	ldr	x0, [x0, #8]
  400a94:	b9400004 	ldr	w4, [x0]
  400a98:	f9400fa0 	ldr	x0, [x29, #24]
  400a9c:	f9400400 	ldr	x0, [x0, #8]
  400aa0:	f9400400 	ldr	x0, [x0, #8]
  400aa4:	f9400400 	ldr	x0, [x0, #8]
  400aa8:	f9400400 	ldr	x0, [x0, #8]
  400aac:	b9400005 	ldr	w5, [x0]
  400ab0:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ab4:	91108000 	add	x0, x0, #0x420
  400ab8:	97fffec2 	bl	4005c0 <printf@plt>
  400abc:	f9400fa0 	ldr	x0, [x29, #24]
  400ac0:	f9400400 	ldr	x0, [x0, #8]
  400ac4:	f9001fa0 	str	x0, [x29, #56]
  400ac8:	f9401fa0 	ldr	x0, [x29, #56]
  400acc:	b9400001 	ldr	w1, [x0]
  400ad0:	f9400fa0 	ldr	x0, [x29, #24]
  400ad4:	f9400402 	ldr	x2, [x0, #8]
  400ad8:	f9400fa0 	ldr	x0, [x29, #24]
  400adc:	f9400400 	ldr	x0, [x0, #8]
  400ae0:	b9400003 	ldr	w3, [x0]
  400ae4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ae8:	9110e000 	add	x0, x0, #0x438
  400aec:	2a0303e4 	mov	w4, w3
  400af0:	aa0203e3 	mov	x3, x2
  400af4:	2a0103e2 	mov	w2, w1
  400af8:	f9401fa1 	ldr	x1, [x29, #56]
  400afc:	97fffeb1 	bl	4005c0 <printf@plt>
  400b00:	f9400fa0 	ldr	x0, [x29, #24]
  400b04:	f900041f 	str	xzr, [x0, #8]
  400b08:	f9400fa0 	ldr	x0, [x29, #24]
  400b0c:	f9400401 	ldr	x1, [x0, #8]
  400b10:	f9400fa0 	ldr	x0, [x29, #24]
  400b14:	b9400002 	ldr	w2, [x0]
  400b18:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400b1c:	91118000 	add	x0, x0, #0x460
  400b20:	97fffea8 	bl	4005c0 <printf@plt>
  400b24:	1400004b 	b	400c50 <reverse_debug+0x2a0>
  400b28:	f9401fa0 	ldr	x0, [x29, #56]
  400b2c:	b9400001 	ldr	w1, [x0]
  400b30:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400b34:	91120000 	add	x0, x0, #0x480
  400b38:	2a0103e2 	mov	w2, w1
  400b3c:	f9401fa1 	ldr	x1, [x29, #56]
  400b40:	97fffea0 	bl	4005c0 <printf@plt>
  400b44:	f9401fa0 	ldr	x0, [x29, #56]
  400b48:	f90017a0 	str	x0, [x29, #40]
  400b4c:	f94017a0 	ldr	x0, [x29, #40]
  400b50:	b9400001 	ldr	w1, [x0]
  400b54:	f9401fa0 	ldr	x0, [x29, #56]
  400b58:	b9400002 	ldr	w2, [x0]
  400b5c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400b60:	91126000 	add	x0, x0, #0x498
  400b64:	2a0203e4 	mov	w4, w2
  400b68:	f9401fa3 	ldr	x3, [x29, #56]
  400b6c:	2a0103e2 	mov	w2, w1
  400b70:	f94017a1 	ldr	x1, [x29, #40]
  400b74:	97fffe93 	bl	4005c0 <printf@plt>
  400b78:	f9401fa0 	ldr	x0, [x29, #56]
  400b7c:	f9400400 	ldr	x0, [x0, #8]
  400b80:	f9001fa0 	str	x0, [x29, #56]
  400b84:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400b88:	91130000 	add	x0, x0, #0x4c0
  400b8c:	f9401fa1 	ldr	x1, [x29, #56]
  400b90:	97fffe8c 	bl	4005c0 <printf@plt>
  400b94:	f9401fa0 	ldr	x0, [x29, #56]
  400b98:	f100001f 	cmp	x0, #0x0
  400b9c:	540000e0 	b.eq	400bb8 <reverse_debug+0x208>  // b.none
  400ba0:	f9401fa0 	ldr	x0, [x29, #56]
  400ba4:	b9400001 	ldr	w1, [x0]
  400ba8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400bac:	91136000 	add	x0, x0, #0x4d8
  400bb0:	97fffe84 	bl	4005c0 <printf@plt>
  400bb4:	14000004 	b	400bc4 <reverse_debug+0x214>
  400bb8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400bbc:	91138000 	add	x0, x0, #0x4e0
  400bc0:	97fffe7c 	bl	4005b0 <puts@plt>
  400bc4:	f9400fa0 	ldr	x0, [x29, #24]
  400bc8:	f9400401 	ldr	x1, [x0, #8]
  400bcc:	f94017a0 	ldr	x0, [x29, #40]
  400bd0:	f9000401 	str	x1, [x0, #8]
  400bd4:	f94017a0 	ldr	x0, [x29, #40]
  400bd8:	f9400401 	ldr	x1, [x0, #8]
  400bdc:	f94017a0 	ldr	x0, [x29, #40]
  400be0:	b9400002 	ldr	w2, [x0]
  400be4:	f9400fa0 	ldr	x0, [x29, #24]
  400be8:	f9400403 	ldr	x3, [x0, #8]
  400bec:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400bf0:	9113a000 	add	x0, x0, #0x4e8
  400bf4:	97fffe73 	bl	4005c0 <printf@plt>
  400bf8:	f9400fa0 	ldr	x0, [x29, #24]
  400bfc:	f94017a1 	ldr	x1, [x29, #40]
  400c00:	f9000401 	str	x1, [x0, #8]
  400c04:	f9400fa0 	ldr	x0, [x29, #24]
  400c08:	f9400401 	ldr	x1, [x0, #8]
  400c0c:	f9400fa0 	ldr	x0, [x29, #24]
  400c10:	f9400400 	ldr	x0, [x0, #8]
  400c14:	b9400002 	ldr	w2, [x0]
  400c18:	f94017a0 	ldr	x0, [x29, #40]
  400c1c:	b9400003 	ldr	w3, [x0]
  400c20:	f94017a0 	ldr	x0, [x29, #40]
  400c24:	f9400404 	ldr	x4, [x0, #8]
  400c28:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400c2c:	91144000 	add	x0, x0, #0x510
  400c30:	aa0403e5 	mov	x5, x4
  400c34:	2a0303e4 	mov	w4, w3
  400c38:	f94017a3 	ldr	x3, [x29, #40]
  400c3c:	97fffe61 	bl	4005c0 <printf@plt>
  400c40:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400c44:	9114e000 	add	x0, x0, #0x538
  400c48:	f9400fa1 	ldr	x1, [x29, #24]
  400c4c:	97fffe5d 	bl	4005c0 <printf@plt>
  400c50:	f9401fa0 	ldr	x0, [x29, #56]
  400c54:	f100001f 	cmp	x0, #0x0
  400c58:	54fff681 	b.ne	400b28 <reverse_debug+0x178>  // b.any
  400c5c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400c60:	91156000 	add	x0, x0, #0x558
  400c64:	f9400fa1 	ldr	x1, [x29, #24]
  400c68:	97fffe56 	bl	4005c0 <printf@plt>
  400c6c:	f9400fa0 	ldr	x0, [x29, #24]
  400c70:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c74:	d65f03c0 	ret

0000000000400c78 <reverse_1>:
  400c78:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400c7c:	910003fd 	mov	x29, sp
  400c80:	f9000fa0 	str	x0, [x29, #24]
  400c84:	f9400fa0 	ldr	x0, [x29, #24]
  400c88:	f9400401 	ldr	x1, [x0, #8]
  400c8c:	f9400fa0 	ldr	x0, [x29, #24]
  400c90:	f9400400 	ldr	x0, [x0, #8]
  400c94:	f9400402 	ldr	x2, [x0, #8]
  400c98:	f9400fa0 	ldr	x0, [x29, #24]
  400c9c:	f9400400 	ldr	x0, [x0, #8]
  400ca0:	f9400400 	ldr	x0, [x0, #8]
  400ca4:	f9400403 	ldr	x3, [x0, #8]
  400ca8:	f9400fa0 	ldr	x0, [x29, #24]
  400cac:	f9400400 	ldr	x0, [x0, #8]
  400cb0:	f9400400 	ldr	x0, [x0, #8]
  400cb4:	f9400400 	ldr	x0, [x0, #8]
  400cb8:	f9400404 	ldr	x4, [x0, #8]
  400cbc:	f9400fa0 	ldr	x0, [x29, #24]
  400cc0:	f9400400 	ldr	x0, [x0, #8]
  400cc4:	f9400400 	ldr	x0, [x0, #8]
  400cc8:	f9400400 	ldr	x0, [x0, #8]
  400ccc:	f9400400 	ldr	x0, [x0, #8]
  400cd0:	f9400405 	ldr	x5, [x0, #8]
  400cd4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400cd8:	9115c000 	add	x0, x0, #0x570
  400cdc:	aa0503e6 	mov	x6, x5
  400ce0:	aa0403e5 	mov	x5, x4
  400ce4:	aa0303e4 	mov	x4, x3
  400ce8:	aa0203e3 	mov	x3, x2
  400cec:	aa0103e2 	mov	x2, x1
  400cf0:	f9400fa1 	ldr	x1, [x29, #24]
  400cf4:	97fffe33 	bl	4005c0 <printf@plt>
  400cf8:	f9400fa0 	ldr	x0, [x29, #24]
  400cfc:	f9400400 	ldr	x0, [x0, #8]
  400d00:	f90017a0 	str	x0, [x29, #40]
  400d04:	f9400fa0 	ldr	x0, [x29, #24]
  400d08:	f9400401 	ldr	x1, [x0, #8]
  400d0c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400d10:	91162000 	add	x0, x0, #0x588
  400d14:	aa0103e2 	mov	x2, x1
  400d18:	f94017a1 	ldr	x1, [x29, #40]
  400d1c:	97fffe29 	bl	4005c0 <printf@plt>
  400d20:	1400002a 	b	400dc8 <reverse_1+0x150>
  400d24:	f94017a0 	ldr	x0, [x29, #40]
  400d28:	f9400400 	ldr	x0, [x0, #8]
  400d2c:	f90013a0 	str	x0, [x29, #32]
  400d30:	f94017a0 	ldr	x0, [x29, #40]
  400d34:	f9400401 	ldr	x1, [x0, #8]
  400d38:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400d3c:	9116a000 	add	x0, x0, #0x5a8
  400d40:	aa0103e2 	mov	x2, x1
  400d44:	f94013a1 	ldr	x1, [x29, #32]
  400d48:	97fffe1e 	bl	4005c0 <printf@plt>
  400d4c:	f94013a0 	ldr	x0, [x29, #32]
  400d50:	f9400401 	ldr	x1, [x0, #8]
  400d54:	f94017a0 	ldr	x0, [x29, #40]
  400d58:	f9000401 	str	x1, [x0, #8]
  400d5c:	f94017a0 	ldr	x0, [x29, #40]
  400d60:	f9400401 	ldr	x1, [x0, #8]
  400d64:	f94013a0 	ldr	x0, [x29, #32]
  400d68:	f9400402 	ldr	x2, [x0, #8]
  400d6c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400d70:	91170000 	add	x0, x0, #0x5c0
  400d74:	97fffe13 	bl	4005c0 <printf@plt>
  400d78:	f9400fa0 	ldr	x0, [x29, #24]
  400d7c:	f9400401 	ldr	x1, [x0, #8]
  400d80:	f94013a0 	ldr	x0, [x29, #32]
  400d84:	f9000401 	str	x1, [x0, #8]
  400d88:	f94013a0 	ldr	x0, [x29, #32]
  400d8c:	f9400401 	ldr	x1, [x0, #8]
  400d90:	f9400fa0 	ldr	x0, [x29, #24]
  400d94:	f9400402 	ldr	x2, [x0, #8]
  400d98:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400d9c:	91178000 	add	x0, x0, #0x5e0
  400da0:	97fffe08 	bl	4005c0 <printf@plt>
  400da4:	f9400fa0 	ldr	x0, [x29, #24]
  400da8:	f94013a1 	ldr	x1, [x29, #32]
  400dac:	f9000401 	str	x1, [x0, #8]
  400db0:	f9400fa0 	ldr	x0, [x29, #24]
  400db4:	f9400401 	ldr	x1, [x0, #8]
  400db8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400dbc:	91180000 	add	x0, x0, #0x600
  400dc0:	f94013a2 	ldr	x2, [x29, #32]
  400dc4:	97fffdff 	bl	4005c0 <printf@plt>
  400dc8:	f94017a0 	ldr	x0, [x29, #40]
  400dcc:	f9400400 	ldr	x0, [x0, #8]
  400dd0:	f100001f 	cmp	x0, #0x0
  400dd4:	54fffa81 	b.ne	400d24 <reverse_1+0xac>  // b.any
  400dd8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ddc:	91188000 	add	x0, x0, #0x620
  400de0:	f9400fa1 	ldr	x1, [x29, #24]
  400de4:	97fffdf7 	bl	4005c0 <printf@plt>
  400de8:	f9400fa0 	ldr	x0, [x29, #24]
  400dec:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400df0:	d65f03c0 	ret

0000000000400df4 <reverse_2>:
  400df4:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400df8:	910003fd 	mov	x29, sp
  400dfc:	f9000fa0 	str	x0, [x29, #24]
  400e00:	f9400fa0 	ldr	x0, [x29, #24]
  400e04:	f9400400 	ldr	x0, [x0, #8]
  400e08:	f9001fa0 	str	x0, [x29, #56]
  400e0c:	f9400fa0 	ldr	x0, [x29, #24]
  400e10:	f9400401 	ldr	x1, [x0, #8]
  400e14:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400e18:	91190000 	add	x0, x0, #0x640
  400e1c:	aa0103e2 	mov	x2, x1
  400e20:	f9401fa1 	ldr	x1, [x29, #56]
  400e24:	97fffde7 	bl	4005c0 <printf@plt>
  400e28:	f9401fa0 	ldr	x0, [x29, #56]
  400e2c:	f9400400 	ldr	x0, [x0, #8]
  400e30:	f9001ba0 	str	x0, [x29, #48]
  400e34:	f9401fa0 	ldr	x0, [x29, #56]
  400e38:	f9400401 	ldr	x1, [x0, #8]
  400e3c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400e40:	91196000 	add	x0, x0, #0x658
  400e44:	aa0103e2 	mov	x2, x1
  400e48:	f9401ba1 	ldr	x1, [x29, #48]
  400e4c:	97fffddd 	bl	4005c0 <printf@plt>
  400e50:	f9401fa0 	ldr	x0, [x29, #56]
  400e54:	f900041f 	str	xzr, [x0, #8]
  400e58:	f9401fa0 	ldr	x0, [x29, #56]
  400e5c:	f9400401 	ldr	x1, [x0, #8]
  400e60:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400e64:	9119e000 	add	x0, x0, #0x678
  400e68:	97fffdd6 	bl	4005c0 <printf@plt>
  400e6c:	14000026 	b	400f04 <reverse_2+0x110>
  400e70:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400e74:	911a4000 	add	x0, x0, #0x690
  400e78:	f9401ba1 	ldr	x1, [x29, #48]
  400e7c:	97fffdd1 	bl	4005c0 <printf@plt>
  400e80:	f9401ba0 	ldr	x0, [x29, #48]
  400e84:	f9400400 	ldr	x0, [x0, #8]
  400e88:	f90017a0 	str	x0, [x29, #40]
  400e8c:	f9401ba0 	ldr	x0, [x29, #48]
  400e90:	f9400401 	ldr	x1, [x0, #8]
  400e94:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400e98:	911a8000 	add	x0, x0, #0x6a0
  400e9c:	aa0103e2 	mov	x2, x1
  400ea0:	f94017a1 	ldr	x1, [x29, #40]
  400ea4:	97fffdc7 	bl	4005c0 <printf@plt>
  400ea8:	f9401ba0 	ldr	x0, [x29, #48]
  400eac:	f9401fa1 	ldr	x1, [x29, #56]
  400eb0:	f9000401 	str	x1, [x0, #8]
  400eb4:	f9401ba0 	ldr	x0, [x29, #48]
  400eb8:	f9400401 	ldr	x1, [x0, #8]
  400ebc:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ec0:	911b0000 	add	x0, x0, #0x6c0
  400ec4:	f9401fa2 	ldr	x2, [x29, #56]
  400ec8:	97fffdbe 	bl	4005c0 <printf@plt>
  400ecc:	f9401ba0 	ldr	x0, [x29, #48]
  400ed0:	f9001fa0 	str	x0, [x29, #56]
  400ed4:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ed8:	911b8000 	add	x0, x0, #0x6e0
  400edc:	f9401ba2 	ldr	x2, [x29, #48]
  400ee0:	f9401fa1 	ldr	x1, [x29, #56]
  400ee4:	97fffdb7 	bl	4005c0 <printf@plt>
  400ee8:	f94017a0 	ldr	x0, [x29, #40]
  400eec:	f9001ba0 	str	x0, [x29, #48]
  400ef0:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400ef4:	911be000 	add	x0, x0, #0x6f8
  400ef8:	f94017a2 	ldr	x2, [x29, #40]
  400efc:	f9401ba1 	ldr	x1, [x29, #48]
  400f00:	97fffdb0 	bl	4005c0 <printf@plt>
  400f04:	f9401ba0 	ldr	x0, [x29, #48]
  400f08:	f100001f 	cmp	x0, #0x0
  400f0c:	54fffb21 	b.ne	400e70 <reverse_2+0x7c>  // b.any
  400f10:	f9400fa0 	ldr	x0, [x29, #24]
  400f14:	f9401fa1 	ldr	x1, [x29, #56]
  400f18:	f9000401 	str	x1, [x0, #8]
  400f1c:	f9400fa0 	ldr	x0, [x29, #24]
  400f20:	f9400401 	ldr	x1, [x0, #8]
  400f24:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400f28:	911c4000 	add	x0, x0, #0x710
  400f2c:	f9401fa2 	ldr	x2, [x29, #56]
  400f30:	97fffda4 	bl	4005c0 <printf@plt>
  400f34:	f9400fa0 	ldr	x0, [x29, #24]
  400f38:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f3c:	d65f03c0 	ret

0000000000400f40 <merge_debug>:
  400f40:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400f44:	910003fd 	mov	x29, sp
  400f48:	f9000fa0 	str	x0, [x29, #24]
  400f4c:	f9000ba1 	str	x1, [x29, #16]
  400f50:	f9400fa0 	ldr	x0, [x29, #24]
  400f54:	f90017a0 	str	x0, [x29, #40]
  400f58:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400f5c:	911cc000 	add	x0, x0, #0x730
  400f60:	f9400ba3 	ldr	x3, [x29, #16]
  400f64:	f9400fa2 	ldr	x2, [x29, #24]
  400f68:	f94017a1 	ldr	x1, [x29, #40]
  400f6c:	97fffd95 	bl	4005c0 <printf@plt>
  400f70:	1400000f 	b	400fac <merge_debug+0x6c>
  400f74:	f94017a0 	ldr	x0, [x29, #40]
  400f78:	f9400401 	ldr	x1, [x0, #8]
  400f7c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400f80:	911d4000 	add	x0, x0, #0x750
  400f84:	aa0103e2 	mov	x2, x1
  400f88:	f94017a1 	ldr	x1, [x29, #40]
  400f8c:	97fffd8d 	bl	4005c0 <printf@plt>
  400f90:	f94017a0 	ldr	x0, [x29, #40]
  400f94:	f9400400 	ldr	x0, [x0, #8]
  400f98:	f90017a0 	str	x0, [x29, #40]
  400f9c:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400fa0:	911dc000 	add	x0, x0, #0x770
  400fa4:	f94017a1 	ldr	x1, [x29, #40]
  400fa8:	97fffd86 	bl	4005c0 <printf@plt>
  400fac:	f94017a0 	ldr	x0, [x29, #40]
  400fb0:	f9400400 	ldr	x0, [x0, #8]
  400fb4:	f100001f 	cmp	x0, #0x0
  400fb8:	54fffde1 	b.ne	400f74 <merge_debug+0x34>  // b.any
  400fbc:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400fc0:	911e2000 	add	x0, x0, #0x788
  400fc4:	f94017a1 	ldr	x1, [x29, #40]
  400fc8:	97fffd7e 	bl	4005c0 <printf@plt>
  400fcc:	f94017a0 	ldr	x0, [x29, #40]
  400fd0:	f9400ba1 	ldr	x1, [x29, #16]
  400fd4:	f9000401 	str	x1, [x0, #8]
  400fd8:	b0000000 	adrp	x0, 401000 <create_circular_link+0x8>
  400fdc:	911e8000 	add	x0, x0, #0x7a0
  400fe0:	f9400fa2 	ldr	x2, [x29, #24]
  400fe4:	f94017a1 	ldr	x1, [x29, #40]
  400fe8:	97fffd76 	bl	4005c0 <printf@plt>
  400fec:	f9400fa0 	ldr	x0, [x29, #24]
  400ff0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ff4:	d65f03c0 	ret

0000000000400ff8 <create_circular_link>:
  400ff8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400ffc:	910003fd 	mov	x29, sp
  401000:	d2800200 	mov	x0, #0x10                  	// #16
  401004:	97fffd5b 	bl	400570 <malloc@plt>
  401008:	f9000fa0 	str	x0, [x29, #24]
  40100c:	f9400fa0 	ldr	x0, [x29, #24]
  401010:	f100001f 	cmp	x0, #0x0
  401014:	540000c1 	b.ne	40102c <create_circular_link+0x34>  // b.any
  401018:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  40101c:	911ee000 	add	x0, x0, #0x7b8
  401020:	97fffd68 	bl	4005c0 <printf@plt>
  401024:	d2800000 	mov	x0, #0x0                   	// #0
  401028:	14000011 	b	40106c <create_circular_link+0x74>
  40102c:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  401030:	911f4000 	add	x0, x0, #0x7d0
  401034:	f9400fa1 	ldr	x1, [x29, #24]
  401038:	97fffd62 	bl	4005c0 <printf@plt>
  40103c:	f9400fa0 	ldr	x0, [x29, #24]
  401040:	b900001f 	str	wzr, [x0]
  401044:	f9400fa0 	ldr	x0, [x29, #24]
  401048:	f9400fa1 	ldr	x1, [x29, #24]
  40104c:	f9000401 	str	x1, [x0, #8]
  401050:	f9400fa0 	ldr	x0, [x29, #24]
  401054:	f9400401 	ldr	x1, [x0, #8]
  401058:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  40105c:	911f8000 	add	x0, x0, #0x7e0
  401060:	f9400fa2 	ldr	x2, [x29, #24]
  401064:	97fffd57 	bl	4005c0 <printf@plt>
  401068:	f9400fa0 	ldr	x0, [x29, #24]
  40106c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401070:	d65f03c0 	ret

0000000000401074 <insert>:
  401074:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  401078:	910003fd 	mov	x29, sp
  40107c:	f9000fa0 	str	x0, [x29, #24]
  401080:	b90017a1 	str	w1, [x29, #20]
  401084:	b9003fbf 	str	wzr, [x29, #60]
  401088:	f9400fa0 	ldr	x0, [x29, #24]
  40108c:	f9001ba0 	str	x0, [x29, #48]
  401090:	f9400fa0 	ldr	x0, [x29, #24]
  401094:	f90027a0 	str	x0, [x29, #72]
  401098:	f9401ba0 	ldr	x0, [x29, #48]
  40109c:	f9400400 	ldr	x0, [x0, #8]
  4010a0:	f90023a0 	str	x0, [x29, #64]
  4010a4:	1400000b 	b	4010d0 <insert+0x5c>
  4010a8:	f94023a0 	ldr	x0, [x29, #64]
  4010ac:	f90027a0 	str	x0, [x29, #72]
  4010b0:	f94023a0 	ldr	x0, [x29, #64]
  4010b4:	f9400400 	ldr	x0, [x0, #8]
  4010b8:	f90023a0 	str	x0, [x29, #64]
  4010bc:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4010c0:	911fe000 	add	x0, x0, #0x7f8
  4010c4:	f94023a2 	ldr	x2, [x29, #64]
  4010c8:	f94027a1 	ldr	x1, [x29, #72]
  4010cc:	97fffd3d 	bl	4005c0 <printf@plt>
  4010d0:	f94023a1 	ldr	x1, [x29, #64]
  4010d4:	f9401ba0 	ldr	x0, [x29, #48]
  4010d8:	eb00003f 	cmp	x1, x0
  4010dc:	54fffe61 	b.ne	4010a8 <insert+0x34>  // b.any
  4010e0:	d2800200 	mov	x0, #0x10                  	// #16
  4010e4:	97fffd23 	bl	400570 <malloc@plt>
  4010e8:	f90017a0 	str	x0, [x29, #40]
  4010ec:	f94017a0 	ldr	x0, [x29, #40]
  4010f0:	f100001f 	cmp	x0, #0x0
  4010f4:	540000c1 	b.ne	40110c <insert+0x98>  // b.any
  4010f8:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4010fc:	91204000 	add	x0, x0, #0x810
  401100:	97fffd30 	bl	4005c0 <printf@plt>
  401104:	d2800000 	mov	x0, #0x0                   	// #0
  401108:	14000015 	b	40115c <insert+0xe8>
  40110c:	f94017a0 	ldr	x0, [x29, #40]
  401110:	b94017a1 	ldr	w1, [x29, #20]
  401114:	b9000001 	str	w1, [x0]
  401118:	f94027a0 	ldr	x0, [x29, #72]
  40111c:	f9400401 	ldr	x1, [x0, #8]
  401120:	f94017a0 	ldr	x0, [x29, #40]
  401124:	f9000401 	str	x1, [x0, #8]
  401128:	f94027a0 	ldr	x0, [x29, #72]
  40112c:	f94017a1 	ldr	x1, [x29, #40]
  401130:	f9000401 	str	x1, [x0, #8]
  401134:	f94027a0 	ldr	x0, [x29, #72]
  401138:	f9400401 	ldr	x1, [x0, #8]
  40113c:	f94017a0 	ldr	x0, [x29, #40]
  401140:	f9400402 	ldr	x2, [x0, #8]
  401144:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  401148:	9120c000 	add	x0, x0, #0x830
  40114c:	aa0203e3 	mov	x3, x2
  401150:	f94017a2 	ldr	x2, [x29, #40]
  401154:	97fffd1b 	bl	4005c0 <printf@plt>
  401158:	f9401ba0 	ldr	x0, [x29, #48]
  40115c:	a8c57bfd 	ldp	x29, x30, [sp], #80
  401160:	d65f03c0 	ret

0000000000401164 <display>:
  401164:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401168:	910003fd 	mov	x29, sp
  40116c:	f9000fa0 	str	x0, [x29, #24]
  401170:	f9400fa0 	ldr	x0, [x29, #24]
  401174:	f90013a0 	str	x0, [x29, #32]
  401178:	f9400fa0 	ldr	x0, [x29, #24]
  40117c:	f9400400 	ldr	x0, [x0, #8]
  401180:	f90017a0 	str	x0, [x29, #40]
  401184:	14000009 	b	4011a8 <display+0x44>
  401188:	f94017a0 	ldr	x0, [x29, #40]
  40118c:	b9400001 	ldr	w1, [x0]
  401190:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  401194:	91216000 	add	x0, x0, #0x858
  401198:	97fffd0a 	bl	4005c0 <printf@plt>
  40119c:	f94017a0 	ldr	x0, [x29, #40]
  4011a0:	f9400400 	ldr	x0, [x0, #8]
  4011a4:	f90017a0 	str	x0, [x29, #40]
  4011a8:	f94017a1 	ldr	x1, [x29, #40]
  4011ac:	f94013a0 	ldr	x0, [x29, #32]
  4011b0:	eb00003f 	cmp	x1, x0
  4011b4:	54fffea1 	b.ne	401188 <display+0x24>  // b.any
  4011b8:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4011bc:	91218000 	add	x0, x0, #0x860
  4011c0:	97fffcfc 	bl	4005b0 <puts@plt>
  4011c4:	d503201f 	nop
  4011c8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4011cc:	d65f03c0 	ret

00000000004011d0 <main>:
  4011d0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4011d4:	910003fd 	mov	x29, sp
  4011d8:	97ffff88 	bl	400ff8 <create_circular_link>
  4011dc:	f9000ba0 	str	x0, [x29, #16]
  4011e0:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  4011e4:	910fa000 	add	x0, x0, #0x3e8
  4011e8:	f9400ba1 	ldr	x1, [x29, #16]
  4011ec:	97fffcf5 	bl	4005c0 <printf@plt>
  4011f0:	52800020 	mov	w0, #0x1                   	// #1
  4011f4:	b9001fa0 	str	w0, [x29, #28]
  4011f8:	14000008 	b	401218 <main+0x48>
  4011fc:	b9401fa1 	ldr	w1, [x29, #28]
  401200:	f9400ba0 	ldr	x0, [x29, #16]
  401204:	97ffff9c 	bl	401074 <insert>
  401208:	f9000ba0 	str	x0, [x29, #16]
  40120c:	b9401fa0 	ldr	w0, [x29, #28]
  401210:	11000400 	add	w0, w0, #0x1
  401214:	b9001fa0 	str	w0, [x29, #28]
  401218:	b9401fa0 	ldr	w0, [x29, #28]
  40121c:	7100281f 	cmp	w0, #0xa
  401220:	54fffeed 	b.le	4011fc <main+0x2c>
  401224:	90000000 	adrp	x0, 401000 <create_circular_link+0x8>
  401228:	910fa000 	add	x0, x0, #0x3e8
  40122c:	f9400ba1 	ldr	x1, [x29, #16]
  401230:	97fffce4 	bl	4005c0 <printf@plt>
  401234:	f9400ba0 	ldr	x0, [x29, #16]
  401238:	97ffffcb 	bl	401164 <display>
  40123c:	52800000 	mov	w0, #0x0                   	// #0
  401240:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401244:	d65f03c0 	ret

0000000000401248 <__libc_csu_init>:
  401248:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40124c:	910003fd 	mov	x29, sp
  401250:	a901d7f4 	stp	x20, x21, [sp, #24]
  401254:	90000094 	adrp	x20, 411000 <__FRAME_END__+0xf79c>
  401258:	90000095 	adrp	x21, 411000 <__FRAME_END__+0xf79c>
  40125c:	91374294 	add	x20, x20, #0xdd0
  401260:	913722b5 	add	x21, x21, #0xdc8
  401264:	a902dff6 	stp	x22, x23, [sp, #40]
  401268:	cb150294 	sub	x20, x20, x21
  40126c:	f9001ff8 	str	x24, [sp, #56]
  401270:	2a0003f6 	mov	w22, w0
  401274:	aa0103f7 	mov	x23, x1
  401278:	9343fe94 	asr	x20, x20, #3
  40127c:	aa0203f8 	mov	x24, x2
  401280:	97fffcae 	bl	400538 <_init>
  401284:	b4000194 	cbz	x20, 4012b4 <__libc_csu_init+0x6c>
  401288:	f9000bb3 	str	x19, [x29, #16]
  40128c:	d2800013 	mov	x19, #0x0                   	// #0
  401290:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  401294:	aa1803e2 	mov	x2, x24
  401298:	aa1703e1 	mov	x1, x23
  40129c:	2a1603e0 	mov	w0, w22
  4012a0:	91000673 	add	x19, x19, #0x1
  4012a4:	d63f0060 	blr	x3
  4012a8:	eb13029f 	cmp	x20, x19
  4012ac:	54ffff21 	b.ne	401290 <__libc_csu_init+0x48>  // b.any
  4012b0:	f9400bb3 	ldr	x19, [x29, #16]
  4012b4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  4012b8:	a942dff6 	ldp	x22, x23, [sp, #40]
  4012bc:	f9401ff8 	ldr	x24, [sp, #56]
  4012c0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4012c4:	d65f03c0 	ret

00000000004012c8 <__libc_csu_fini>:
  4012c8:	d65f03c0 	ret

Disassembly of section .fini:

00000000004012cc <_fini>:
  4012cc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4012d0:	910003fd 	mov	x29, sp
  4012d4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4012d8:	d65f03c0 	ret
